This invention relates generally to clock boundary sampling and more particularly to the obtaining even distributions of samples across differing clock domain boundaries.
Present generations of microprocessors typically include multiple clock boundaries that are situated both on and off chip. Data sampling hardware facilities that are dedicated to sampling data relating to the state of a processor during the execution of applications are affected by these varying clock boundaries. In general, a clock signal that is originated by a partition within a processing system comprising a clock boundary of a variable X-to-1 clock boundary is returned to a data capture component of the microprocessor, wherein the data capture component typically operates on a 1-to-1 clock boundary. The data capture aspect is controlled by a programmable sampling pulse, wherein it is usually specified that a predetermined number of cycles be executed between sampled pulses. The data capture hardware configures a cycle countdown value to be a predetermined value and thereafter decrements the value for each cycle until the value reaches zero (0). As a result of the completed countdown cycle a sample pulse is generated and the countdown value is reset to the predetermined value.
Generated sample pulses are time based in order to avoid any biases towards or away from system events. However unless this pulse is evenly spread across all clock boundaries the signals coming from other than a 1-to-1 clock boundary will be biased in a more subtle way. For example, assume that a 2-to-1 clock boundary segment of a computing system always returns its clocking signals on an even cycle. Therefore, a sample pulse that correlates to the even cycle will sample 2× the signal being high versus the actually signal. And further, a sample pulse that correlates to an odd cycle will never sample the signal being high.
Previously, this issue was solved by forcing a sample rate to be such that a sample pulse would be evenly distributed across all clock boundaries. Thus, in the 2-to-1 clock boundary example the sample rate would be compensated to ensure that the sample pulse toggled between an even or odd cycle. This solution works well as long as the sampling hardware continuously runs during the measurement period and the number of clock boundaries within the system is small. In the presence of multiple partitions that each want to control their sampling independently and multiple clock boundaries that make selecting an appropriate sample rate more difficult, additional hardware is needed to enforce a uniform distribution of sample pulses across clock boundaries.
Any mechanism that relies solely on saving/restoring operation by firmware of cycles to the next sample pulse on partition change is vulnerable to any biases that are introduced by the process of entering a new partition. Thus, a new partition could always enter on a particular clock boundary and bias its next sample pulse towards certain clock boundaries.